The present invention relates, in general, to electronics, and more particularly, to semiconductors, structures thereof, and methods of forming semiconductor devices.
In the past, the electronics industry utilized various methods and structures to form semiconductor devices that included both a silicon metal oxide semiconductor (MOS) field effect transistor (FET) connected in a circuit with a gallium nitride (GaN) transistor. One example of a circuit that includes a GAN and a MOS FET is described in United States patent publication number 2013/0088280 of inventors Lal et al. that was published on Apr. 11, 2013.
In some applications that utilize a device that includes a silicon MOSFET and a GaN transistor, transient voltages can occur that can result in damaging the device. For example, when a signal is applied to disable or switch off the MOS transistor, the voltage on the drain of the transistor may change which can cause transient voltages on the gate electrode of the MOS transistor. In some cases, these transient voltages may be referred to as gate voltage bounce. Under some conditions, the transient voltages can result in unintentional enabling of the MOS transistor when the MOS transistor should be disabled. This unintentional enabling can result in shoot-through currents that could either cause increased power dissipation or could damage either one or both of the MOS transistor or the GAN transistor.
Additionally, in some configurations the GAN transistor may have a large leakage current. When both the GAN transistor and the MOS FET are disabled, the leakage current from the GAN transistor can result in a large drain-to-source voltage (Vds) being formed across the MOS transistor. In some cases, this large Vds voltage can reach the avalanche breakdown voltage of the MOS transistor which may eventually weaken the MOS transistor and/or cause a long-term reliability problem or even result in damaging the MOS transistor.
Accordingly, it is desirable to have a semiconductor device that includes a MOS transistor with reduced sensitivity to transient voltages on the gate electrode such as for example during disabling of the MOS transistor, or that can minimize damaged from current applied to the MOS transistor.
For simplicity and clarity of the illustration(s), elements in the figures are not necessarily to scale, some of the elements may be exaggerated for illustrative purposes, and the same reference numbers in different figures denote the same elements, unless stated otherwise. Additionally, descriptions and details of well-known steps and elements may be omitted for simplicity of the description. As used herein current carrying element or current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control element or control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Additionally, one current carrying element may carry current in one direction through a device, such as carry current entering the device, and a second current carrying element may carry current in an opposite direction through the device, such as carry current leaving the device. Although the devices may be explained herein as certain N-channel or P-channel devices, or certain N-type or P-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. One of ordinary skill in the art understands that the conductivity type refers to the mechanism through which conduction occurs such as through conduction of holes or electrons, therefore, that conductivity type does not refer to the doping concentration but the doping type, such as P-type or N-type. It will be appreciated by those skilled in the art that the words during, while, and when as used herein relating to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay(s), such as various propagation delays, between the reaction that is initiated by the initial action. Additionally, the term while means that a certain action occurs at least within some portion of a duration of the initiating action. The use of the word approximately or substantially means that a value of an element has a parameter that is expected to be close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to at least ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are reasonable variances from the ideal goal of exactly as described. When used in reference to a state of a signal, the term “asserted” means an active state of the signal and the term “negated” means an inactive state of the signal. The actual voltage value or logic state (such as a “1” or a “0”) of the signal depends on whether positive or negative logic is used. Thus, asserted can be either a high voltage or a high logic or a low voltage or low logic depending on whether positive or negative logic is used and negated may be either a low voltage or low state or a high voltage or high logic depending on whether positive or negative logic is used. Herein, a positive logic convention is used, but those skilled in the art understand that a negative logic convention could also be used. The terms first, second, third and the like in the claims or/and in the Detailed Description of the Drawings, as used in a portion of a name of an element are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operation in other sequences than described or illustrated herein. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but in some cases it may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art, in one or more embodiments. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants the edges of doped regions generally may not be straight lines and the corners may not be precise angles.
In addition, the description illustrates a cellular design (where the body regions are a plurality of cellular regions) instead of a single body design (where the body region is comprised of a single region formed in an elongated pattern, typically in a serpentine pattern). However, it is intended that the description is applicable to both a cellular implementation and a single base implementation.